1. The Field of the Invention
The present invention relates the manufacture of a semiconductor device on a substrate assembly, where the substrate assembly is a substrate having one or more layers or structures formed thereon. More specifically, the present invention relates to the fabrication of a polysilicon structure used in the manufacture of a semiconductor device on a substrate assembly. Even more specifically, the present invention relates to techniques for improving the conductivities of a silicided gate structure and a silicided interconnect structure on a substrate assembly.
2. The Relevant Technology
Polycrystalline silicon (polysilicon) is the preferred material for gate electrodes in MOSFET structures. Polysilicon is advantageous over metal gate electrodes as it can withstand much higher subsequent processing temperatures before eutectic temperatures are reached. Polysilicon is readily deposited on bulk silicon or SiO2 using low pressure chemical vapor deposition (LPCVD), and the resistivities of doped polysilicon films are less than those of doped epitaxial or bulk silicon layers.
As the drive toward integrating more active devices on a single integrated circuit necessitates the fabrication of increasingly small MOSFET structures, the resistance of the MOSFET gate becomes a limiting factor in device speed. As such, it is beneficial to use materials with the lowest possible sheet resistivities for making contact with the polysilicon gate structure. To this end it is well known that refractory metal suicides can be readily formed on polysilicon MOSFET gate structures using conventional sputtering, deposition, and annealing processes. The refractory metal silicides have low sheet resistivities after annealing and also form low resistance ohmic contacts with commonly used interconnect metals.
Of all the available suicides, titanium disilicide (TiSi2) is preferred due to its inherent low sheet resistivity when annealed to the C54 crystalline phase thereof. To obtain the desired low resistivity requires high temperature annealing in a range from about 700xc2x0 C. to about 1100xc2x0 C. Numerous techniques for creating TiSi2 films on MOSFET gate, source, and drain electrodes are used to obtain the desired low sheet resistivity. An example of such a technique is the chemical vapor deposition (CVD) of either pure titanium metal or stoichiometric titanium silicide (TiSix), with subsequent annealing steps to convert the layer to TiSi2 in the C54 crystalline phase thereof.
Limitations are known to exist with respect to the processing of TiSix films, particularly as MOSFET transistor geometries are scaled down to deep submicron dimensions. It is known that the lowest obtainable sheet resistivities of annealed TiSi2 films are only achieved when the silicide completely transforms to the C54 crystalline phase. It has more recently been discovered that achieving complete C54 crystalline phase transformation as conductor line width dimensions are scaled below about 0.5 microns requires increasingly higher processing temperatures. Such higher processing temperatures create problems such as induced layer defects due to the agglomeration of the silicided metal, and other problems. An agglomeration of a TiSix film on a polysilicon gate having a length below about 0.25 microns can cause an increase in resistance from a normal 1-2 Ohms per square to 20-30 times the resistance.
Accordingly, it would be an advance in the art to fabricate semiconductor interconnects, conductors, and transistor gates using established, reliable processing methods and materials, each of which have a suitably low resistivity so that overall semiconductor device speed and performance is maintained when such structures are scaled down to deep submicron dimensions.
The present invention describes novel methods of making gate structures and interconnect line structures having complex surfaces, which are useful in the fabrication of semiconductor devices. The geometries of the structures, when combined with fabrication methods disclosed, provide for significantly increased areas of exposed polysilicon or amorphous silicon material on which refractory metal layers can be deposited. As such, there is a significant increase in the total cross-sectional area of the regions over which polycide regions (e.g. refractory metal silicides) may potentially be formed in subsequent annealing steps. The increased cross-sectional area of the polycide regions compensates for the increase in polycide sheet resistivity which is observed as semiconductor device geometries are scaled to deep submicron line widths, thereby reducing the effective series resistance of the gate or conductor line structures and of the contact interfaces thereto. Furthermore, when the refractory metal layer consists of titanium metal or as-deposited titanium silicide, the increased surface area may contribute to a lowering of processing temperatures required to achieve a complete transformation of the titanium silicide to the C54 crystalline phase, thereby lowering the overall sheet resistivity in addition to increasing the surface area. The increase in surface area of polycide regions can be accomplished by forming various structures having surfaces upon which the polycide regions are formed.